OzVM  Preliminary Description of the Machine, Opcodes, and Instructions
OzVM is a simple registerbased, RISCstyle processor. The machine maintains 256 generalpurpose 64bit registers, one 32bit instruction pointer, and a 32bit addressable memory region. The specification defines 120 operations supporting 10 data types, covering 4 sizes of integers and 2 sizes of floatingpoint numbers. Any register may be used for either integer or floatingpoint calculations.
Memory access to the valid memory is enforced  access outside that memory results in undefined behavior. The specific amount of memory available to the machine is unspecified. Currently, available memory is fixed at loadtime with no support for runtime memory allocation.
Absent from the machine specification is any native support for interrupts, exceptions, or multithreading. That includes no support for ALU and FPU exceptions such as overflow, underflow, etc.
Registers  Description  

031  Integer / pointer  
 
3263  Floatingpoint  
 
6465  Reserved for compiler  
66255  Unused 
Each opcode is a 32bit field describing the operation and the registers, possibly followed by a 32bit immediate value.
Mandatory  Contingent  



There are ten fundamental types. Each instruction supports some subset of these types.
Type  Description  ILP32 Ctype 

I1  8bit signed integer  char 
I2  16bit signed integer  short 
I4  32bit signed integer  int 
I8  64bit signed integer  long long 
F4  32bit floatingpoint  float 
F8  64bit floatingpoint  double 
U1  8bit unsigned integer  unsigned char 
U2  16bit unsigned integer  unsigned short 
U4  32bit unsigned integer  unsigned int 
U8  64bit unsigned integer  unsigned long long 
There are 120 unique opcodes, one for each type of instruction. Note, the copy to register instructions (C_R_...) on 8bit and 16bit types (I1, I2, U1, U2) always write a full 32bits to the destination register, zero or signextended as appropriate.
Instruction  Types  Operation  Description 

Nop  n/a  none  No operation 
C_R_R  I1, I2, U1, U2, U4, U8  REG(r1) = REG(r2)  Copy to register from register 
C_R_I  I1, I2, U1, U2, U4  REG(r1) = imm  Copy to register from immediate 
C_R_MRI  I1, I2, U1, U2, U4, U8  REG(r1) = MEM( REG(r2) + imm )  Copy to register from memory at register+immediate 
C_R_MRR  I1, I2, U1, U2, U4, U8  REG(r1) = MEM( REG(r2) + REG(r3) )  Copy to register from memory at register+register 
C_MRI_R  U1, U2, U4, U8  MEM( REG(r1) + imm ) = REG(r2)  Copy to memory at register+immediate from register 
C_MRR_R  U1, U2, U4, U8  MEM( REG(r1) + REG(r2) ) = REG(r3)  Copy to memory at register+register from register 
Cvt_F4  F8, I4, I8, U4, U8  (F4)REG(r1) = (type)REG(r2)  Convert to F4 from (type) 
Cvt_F8  F4, I4, I8, U4, U8  (F8)REG(r1) = (type)REG(r2)  Convert to F8 from (type) 
Cvt_U4  F4, F8, U8  (U4)REG(r1) = (type)REG(r2)  Convert to U4 from (type) 
Cvt_U8  F4, F8, I4, U4  (U8)REG(r1) = (type)REG(r2)  Convert to U8 from (type) 
Add  F4, F8, U4, U8  REG(r1) = REG(r2) + REG(r3)  Add 
Sub  F4, F8, U4, U8  REG(r1) = REG(r2)  REG(r3)  Subtract 
Mul  F4, F8, I4, I8, U4, U8  REG(r1) = REG(r2) * REG(r3)  Multiply 
Div  F4, F8, I4, I8, U4, U8  REG(r1) = REG(r2) / REG(r3)  Divide 
Mod  I4, I8, U4, U8  REG(r1) = REG(r2) % REG(r3)  Modulo 
Neg  F4, F8, I4, I8  REG(r1) =  REG(r2)  Negate 
And  U4, U8  REG(r1) = REG(r2) & REG(r3)  Binary and 
Or  U4, U8  REG(r1) = REG(r2)  REG(r3)  Binary or 
Xor  U4, U8  REG(r1) = REG(r2) ^ REG(r3)  Binary exclusiveor 
Com  U4, U8  REG(r1) = ~ REG(r2)  Binary compliment 
Lsh  U4, U8  REG(r1) = REG(r2) << REG(r3)  Leftshift variable number of bits 
Rsh  I4, I8, U4, U8  REG(r1) = REG(r2) >> REG(r3)  Rightshift variable number of bits 
Lsh_C  U4, U8  REG(r1) = REG(r2) << r3  Leftshift constant number of bits 
Rsh_C  I4, I8, U4, U8  REG(r1) = REG(r2) >> r3  Rightshift constant number of bits 
Jump  U4  IP = imm if r1 == 0 IP = REG(r1) otherwise 
Load instruction pointer with new value 
Link  U4  REG(r2) = address of next instruction, then execute Jump 
Copy instruction pointer of next instruction, then jump 
Beq  F4, F8, U4, U8  if REG(r2) == REG(r3) then IP += imm  Branch if equal 
Bne  F4, F8, U4, U8  if REG(r2) != REG(r3) then IP += imm  Branch if notequal 
Ble  F4, F8, I4, I8, U4, U8  if REG(r2) <= REG(r3) then IP += imm  Branch if lessthan or equal 
Blt  F4, F8, I4, I8, U4, U8  if REG(r2) < REG(r3) then IP += imm  Branch if lessthan 
Trap  U4  call system function REG(r1) argument in REG(r2) 
Trap, call system function 
$Revision: 1.1.1.1 $ $Date: 2001/09/18 10:45:25 $